SIST EN 61964:2002

SLOVENSKI STANDARD
SIST EN 61964:2002
01-september-2002
Integrated circuits - Memory devices pin configurations
Integrated circuits - Memory devices pin configurations
Integrierte Schaltungen - Kontaktanordnungen für Speicherbauelemente
Circuits intégrés - Configuration de broches de mémoires
Ta slovenski standard je istoveten z: EN 61964:1999
ICS:
31.200 Integrirana vezja, Integrated circuits.
mikroelektronika Microelectronics
SIST EN 61964:2002 en
2003-01.Slovenski inštitut za standardizacijo. Razmnoževanje celote ali delov tega standarda ni dovoljeno.

---------------------- Page: 1 ----------------------

SIST EN 61964:2002

---------------------- Page: 2 ----------------------

SIST EN 61964:2002

---------------------- Page: 3 ----------------------

SIST EN 61964:2002

---------------------- Page: 4 ----------------------

SIST EN 61964:2002

---------------------- Page: 5 ----------------------

SIST EN 61964:2002

---------------------- Page: 6 ----------------------

SIST EN 61964:2002
NORME
CEI
INTERNATIONALE
IEC
61964
INTERNATIONAL
Première édition
STANDARD
First edition
1999-04
Circuits intégrés –
Configuration de broches de mémoires
Integrated circuits –
Memory devices pin configurations
 IEC 1999 Droits de reproduction réservés  Copyright - all rights reserved
Aucune partie de cette publication ne peut être reproduite ni No part of this publication may be reproduced or utilized in
utilisée sous quelque forme que ce soit et par aucun any form or by any means, electronic or mechanical,
procédé, électronique ou mécanique, y compris la photo- including photocopying and microfilm, without permission in
copie et les microfilms, sans l'accord écrit de l'éditeur. writing from the publisher.
International Electrotechnical Commission 3, rue de Varembé Geneva, Switzerland
Telefax: +41 22 919 0300 e-mail: inmail@iec.ch IEC web site http: //www.iec.ch
CODE PRIX
Commission Electrotechnique Internationale
PRICE CODE R
International Electrotechnical Commission
Pour prix, voir catalogue en vigueur
For price, see current catalogue

---------------------- Page: 7 ----------------------

SIST EN 61964:2002
61964 © IEC:1999 – 3 –
CONTENTS
Page
FOREWORD . 5
INTRODUCTION .7
Clause
1 Scope . 9
2 Normative references . 9
3 Terms and definitions. 9
4 Pin Configurations Catalogue . 21
4.1 Integrated Circuit Dynamic Read/Write Memories . 21
4.2 Integrated Circuit Synchronous Dynamic Read/Write Memories . 23
4.3 Integrated Circuit Static Read/Write Memories. 23
4.4 Integrated Circuit Read-Only Memories . 23
4.5 Integrated Circuit Programmable Read-Only Memories. 23
4.6 MOS Ultraviolet Light Erasable and Programmable Read-Only Memories. 23
4.7 Integrated Circuit Electrically Erasable and Programmable Read-Only Memories . 23
4.8 Memory Modules Comprising Integrated Circuit Memories . 23
Annex A (informative) Bibliography . 39
Table 1 – Nibble wide organization DRAM. 25
Table 2 – Byte wide organization DRAM. 27
Table 3 – Word wide organization DRAM (1) . 29
Table 4 – Word wide organization DRAM (2) . 31
Table 5 – Nibble wide organization SDRAM . 33
Table 6 – Byte wide organization SDRAM . 35
Table 7 – Word wide organization SDRAM . 37

---------------------- Page: 8 ----------------------

SIST EN 61964:2002
61964 © IEC:1999 – 5 –
INTERNATIONAL ELECTROTECHNICAL COMMISSION
–––––––––––––
INTEGRATED CIRCUITS –
MEMORY DEVICES PIN CONFIGURATIONS
FOREWORD
1) The IEC (International Electrotechnical Commission) is a worldwide organization for standardization comprising
all national electrotechnical committees (IEC National Committees). The object of the IEC is to promote
international co-operation on all questions concerning standardization in the electrical and electronic fields. To
this end and in addition to other activities, the IEC publishes International Standards. Their preparation is
entrusted to technical committees; any IEC National Committee interested in the subject dealt with may
participate in this preparatory work. International, governmental and non-governmental organizations liaising
with the IEC also participate in this preparation. The IEC collaborates closely with the International Organization
for Standardization (ISO) in accordance with conditions determined by agreement between the two
organizations.
2) The formal decisions or agreements of the IEC on technical matters express, as nearly as possible, an
international consensus of opinion on the relevant subjects since each technical committee has representation
from all interested National Committees.
3) The documents produced have the form of recommendations for international use and are published in the form
of standards, technical reports or guides and they are accepted by the National Committees in that sense.
4) In order to promote international unification, IEC National Committees undertake to apply IEC International
Standards transparently to the maximum extent possible in their national and regional standards. Any
divergence between the IEC Standard and the corresponding national or regional standard shall be clearly
indicated in the latter.
5) The IEC provides no marking procedure to indicate its approval and cannot be rendered responsible for any
equipment declared to be in conformity with one of its standards.
6) Attention is drawn to the possibility that some of the elements of this International Standard may be the subject
of patent rights. The IEC shall not be held responsible for identifying any or all such patent rights.
International Standard IEC 61964 has been prepared by subcommittee 47A: Integrated circuits,
of IEC technical committee 47: Semiconductor devices.
The text of this standard is based on the following documents:
FDIS Report on voting
47A/535/FDIS 47A/549/RVD
Full information on the voting for the approval of this standard can be found in the report on
voting indicated in the above table.
Annex A is for information only.

---------------------- Page: 9 ----------------------

SIST EN 61964:2002
61964 © IEC:1999 – 7 –
INTRODUCTION
The registration and standardization of the mechanical outlines for integrated memory circuit
devices is an ongoing activity covered in the IEC 60191 series.
Due to the fact that the same mechanical package can house different types of memory
devices, and because the same memory device can be incorporated into different types of
mechanical packages, the number of such configurations has to be limited to minimum
required by the electronics industry. Registration and standardization of such electrical pinout
configurations also helps to establish and maintain compatibility of devices from different
vendors and in different applications.
Owing to the nature of the integrated memory circuits business, in which there is ongoing
potential for the development of new density generations and new electrical functions, this
International Standard has to take the form of an open Standard. In the present context, this
signifies that the new items can be added at any time to any of its clauses. New subclauses
may be created as new types of memory devices come into usage in the industry.
Additions, deletions and any changes will be subject to agreement in order to become effective
for publication.

---------------------- Page: 10 ----------------------

SIST EN 61964:2002
61964 © IEC:1999 – 9 –
INTEGRATED CIRCUITS –
MEMORY DEVICES PIN CONFIGURATIONS
1 Scope
This International Standard applies to pinout package configurations of solid state integrated
circuit memory devices. The purpose of this standard is to establish a registration procedure
for such configurations.
2 Normative references
The following normative documents contain provisions which, through reference in this text,
constitute provisions of this International Standard. For dated references, subsequent
amendments to, or revisions of, any of these publications do not apply. However, parties to
agreements based on this International Standard are encouraged to investigate the possibility
of applying the most recent editions of the normative documents indicated below. For undated
references, the latest edition of the normative document referred to applies. Members of IEC
and ISO maintain registers of currently valid International Standards.
IEC 60191-2:1996, Mechanical standardization of semiconductor devices – Part 2: Dimensions
IEC 60748-1:1984, Semiconductor devices – Integrated circuits – Part 1: General
3 Terms and definitions
For the purpose of this International Standard, the following terms and definitions apply. This
contains definitions of a number of terms that are needed for a clear understanding of the
standard.
Most of these terms have been developed within the semiconductor memory industry. They are
given for quick reference and are not intended to supersede any existing definitions in previous
IEC publications such as IEC 60748-1.
The following pin names and functional descriptions apply uniformly to all devices covered by
this standard. Where a pin has a dual function, and those functions are invoked at substantially
different times, the names and symbols for these functions are separated by a slash (/) (e.g.
V /G\). Where a pin has multiple functions which are used simultaneously, the slash is
PP
omitted (e.g. DQ). Where multiple pins have a similar function, a number symbolised as (n) is
appended to the symbol. Where the pin function has an inverted logic sense, that is, the
function is true or invoked for a low signal, the reverse slash (\) is appended to the symbol.
Where alternative functions are permitted by this standard, these authorized functions are
listed and separated by commas. Where common usage has resulted in two terms being used
interchangeably, both are listed but the less favoured term is enclosed in parentheses.

---------------------- Page: 11 ----------------------

SIST EN 61964:2002
61964 © IEC:1999 – 11 –
3.1 Device pin names
3.1.1 A(n), ADDRESS INPUTS
Those inputs that select (address) a particular cell or set of cells within a memory array for
storage of data or for presentation of the stored data on the device outputs.
The integer (n) serves to differentiate the address inputs one from another.
3.1.2 AL, AL\, ADDRESS LATCH ENABLE
An input that, when true, allows the input address to be entered into a register, and when false,
causes the address state previously entered to be latched.
3.1.3 BA, BANK ADDRESS
In a RAM that has multiple banks in its architecture, the BANK ADDRESS is used, at any
instant of time, to select any one of the available banks.
3.1.4 CA, COLUMN ADDRESS
In an address multiplexed DRAM (dynamic RAM), the address field that is captured by the
COLUMN ENABLE clock CAS\.
3.1.5 CAS, CAS\, COLUMN ENABLE
An enable signal that on some dynamic RAMs actuates only the column-oriented internal
circuits and the data input/output circuits. Most devices normally require the RAS\ signal to be
present for the CAS\ signal to be effective. In some newer designs, however, special
sequences of the RAS\ and CAS\ signals are used to actuate certain special device control
functions.
3.1.6 CK, CK\, INPUT AND OUTPUT CLOCK
An input that controls the activation of both input and output circuitry, normally storage
registers or latches.
3.1.7 CKE, CLOCK ENABLE
In certain synchronous memory devices, a logic level input that enables the clock input and
allows it to fulfill its defined function.
3.1.8 D(n), DATA INPUT
Those inputs whose state represents the value of data that is to be written into the selected
address on a write cycle of an alterable memory device.
3.1.9 DQ(n), DATA INPUT/OUTPUT
The pins that serve as data output(s) when in the read mode and as data input(s) when in the
write mode. When the device is not selected or enabled, the output(s) are in a floating state.

---------------------- Page: 12 ----------------------

SIST EN 61964:2002
61964 © IEC:1999 – 13 –
On a device which has both serial and parallel access ports, these pins provide access to the
parallel RAM port data channels. The suffix (n) is a numeric value indicating the number
assignment of a particular pin with numbering starting at 0. In some situations the letters U or L
are used to indicate that the pins are assigned to the upper or lower byte of a two-byte data
interface. In devices where the standard supports an optional 9th bit that may be used as a
parity bit, the suffix P may be used in lieu of a numeric value.
3.1.10 DQM, DATA INPUT/OUTPUT MASK
A control signal used primarily on SDRAMs that acts as a byte mask for reading and writing
functions. In some instances, the term includes a prefix "U" or "L" to indicating upper or lower
byte control.
3.1.11 G, G\, OUTPUT ENABLE
The input that, when false, disables the outputs and causes them into an inactive state. That
does not affect the write function. When disabled, the inactive state corresponds to floating
state (high impedance), for MOS and TTL devices.
3.1.12 L, LOWER BYTE
When L is used in conjunction with a data or control term it signifies that the combined term
applies to the lower byte of a two-byte data interface device (e.g. LW).
3.1.13 NC, NO CONNECTION
A pin at which no internal electrical connection is present in the chip.
3.1.14 Q(n), DATA OUTPUT
The outputs whose state represents the data read from the selected cells. When the device is
not selected or enabled, the outputs are usually in a floating (Z, high impedance) state.
3.1.15 RA, ROW ADDRESS
In an address multiplexed DRAM, the address field that is captured by the ROW ENABLE
clock, RAS\.
3.1.16 RAS, RAS\, ROW ENABLE
A chip enable signal that, on certain dynamic RAMs, actuates only the row oriented internal
circuitry.
3.1.17 S(n), S(n)\, CHIP SELECT
The input that, when any one is false, causes the device to be disabled without any significant
change in the power consumption. When disabled, the device becomes insensitive to any
command.

---------------------- Page: 13 ----------------------

SIST EN 61964:2002
61964 © IEC:1999 – 15 –
3.1.18 U, UPPER BYTE
When U is used in conjunction with a data or control term it signifies that the combined term
applies to the upper byte of a two-byte data interface device (e.g. UW).
3.1.19 W, W\, WRITE ENABLE
The input that, when true, causes the data present on the D or the DQ pin(s) to be written into
the address cell(s) of the device.
3.2 Power Pin Names
The following symbols are used
...