SIST EN 62418:2010

SLOVENSKI STANDARD
SIST EN 62418:2010
01-september-2010
Polprevodniški elementi - Preskus brez upoštevanja obremenitve metalizacije (IEC
62418:2010)
Semiconductor devices - Metallization stress void test (IEC 62418:2010)
Halbleiterbauelemente - Prüfverfahren zur Metallisierungs-Stressmigration (IEC
62418:2010)
Dispositifs à semi-conducteurs - Essai sur les cavités dues aux contraintes de la
métallisation (CEI 62418:2010)
Ta slovenski standard je istoveten z: EN 62418:2010
ICS:
31.080.01 Polprevodniški elementi Semiconductor devices in
(naprave) na splošno general
SIST EN 62418:2010 en
2003-01.Slovenski inštitut za standardizacijo. Razmnoževanje celote ali delov tega standarda ni dovoljeno.

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SIST EN 62418:2010

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SIST EN 62418:2010

EUROPEAN STANDARD
EN 62418

NORME EUROPÉENNE
July 2010
EUROPÄISCHE NORM

ICS 31.080


English version


Semiconductor devices -
Metallization stress void test
(IEC 62418:2010)


Dispositifs à semi-conducteurs -  Halbleiterbauelemente -
Essai sur les cavités dues aux contraintes Prüfverfahren zur Metallisierungs-
de la métallisation Stressmigration
(CEI 62418:2010) (IEC 62418:2010)




This European Standard was approved by CENELEC on 2010-07-01. CENELEC members are bound to comply
with the CEN/CENELEC Internal Regulations which stipulate the conditions for giving this European Standard
the status of a national standard without any alteration.

Up-to-date lists and bibliographical references concerning such national standards may be obtained on
application to the Central Secretariat or to any CENELEC member.

This European Standard exists in three official versions (English, French, German). A version in any other
language made by translation under the responsibility of a CENELEC member into its own language and notified
to the Central Secretariat has the same status as the official versions.

CENELEC members are the national electrotechnical committees of Austria, Belgium, Bulgaria, Croatia, Cyprus,
the Czech Republic, Denmark, Estonia, Finland, France, Germany, Greece, Hungary, Iceland, Ireland, Italy,
Latvia, Lithuania, Luxembourg, Malta, the Netherlands, Norway, Poland, Portugal, Romania, Slovakia, Slovenia,
Spain, Sweden, Switzerland and the United Kingdom.

CENELEC
European Committee for Electrotechnical Standardization
Comité Européen de Normalisation Electrotechnique
Europäisches Komitee für Elektrotechnische Normung

Management Centre: Avenue Marnix 17, B - 1000 Brussels


© 2010 CENELEC - All rights of exploitation in any form and by any means reserved worldwide for CENELEC members.
Ref. No. EN 62418:2010 E

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SIST EN 62418:2010
EN 62418:2010 - 2 -
Foreword
The text of document 47/2043/FDIS, future edition 1 of IEC 62418, prepared by IEC TC 47,
Semiconductor devices, was submitted to the IEC-CENELEC parallel vote and was approved by
CENELEC as EN 62418 on 2010-07-01.
Attention is drawn to the possibility that some of the elements of this document may be the subject of
patent rights. CEN and CENELEC shall not be held responsible for identifying any or all such patent
rights.
The following dates were fixed:
– latest date by which the EN has to be implemented
at national level by publication of an identical
(dop) 2011-04-01
national standard or by endorsement
– latest date by which the national standards conflicting
(dow) 2013-07-01
with the EN have to be withdrawn
__________
Endorsement notice
The text of the International Standard IEC 62418:2010 was approved by CENELEC as a European
Standard without any modification.
__________

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SIST EN 62418:2010
IEC 62418
®
Edition 1.0 2010-04
INTERNATIONAL
STANDARD
NORME
INTERNATIONALE


Semiconductor devices – Metallization stress void test

Dispositifs à semiconducteurs – Essai sur les cavités dues aux contraintes
de la métallisation

INTERNATIONAL
ELECTROTECHNICAL
COMMISSION
COMMISSION
ELECTROTECHNIQUE
PRICE CODE
INTERNATIONALE
Q
CODE PRIX
ICS 31.080 ISBN 978-2-88910-697-4
® Registered trademark of the International Electrotechnical Commission
Marque déposée de la Commission Electrotechnique Internationale

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SIST EN 62418:2010
– 2 – 62418 © IEC:2010
CONTENTS
FOREWORD.3
1 Scope.5
2 Test equipment.5
3 Test structure .5
3.1 Test structure patterns .5
3.2 Line pattern.5
3.3 Via chain pattern .5
3.3.1 Pattern types .5
3.3.2 Pattern for aluminium (Al) process.5
3.3.3 Pattern for copper (Cu) process.6
4 Stress temperature.6
5 Procedure .6
5.1 Stress void evaluation methods .6
5.2 Resistance measurement method.6
5.3 Inspection method .7
6 Failure criteria .8
6.1 Resistance method.8
6.2 Inspection method .8
7 Data interpretation and lifetime extrapolation (resistance change method).8
8 Items to be specified and reported.9
8.1 Resistance change method .9
8.2 Inspection method .10
Annex A (informative) Stress migration mechanism .11
Annex B (informative) Technology-dependent factors for aluminium .13
Annex C (informative) Technology-dependent factors for copper .14
Annex D (informative) Precautions.15
Bibliography.17

Figure A.1 – Schematic representation of the stress-void formation mechanism in Al.11

Table 1 – Void classification .7

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SIST EN 62418:2010
62418 © IEC:2010 – 3 –
INTERNATIONAL ELECTROTECHNICAL COMMISSION
____________

SEMICONDUCTOR DEVICES –
METALLIZATION STRESS VOID TEST


FOREWORD
1) The International Electrotechnical Commission (IEC) is a worldwide organization for standardization comprising
all national electrotechnical committees (IEC National Committees). The object of IEC is to promote
international co-operation on all questions concerning standardization in the electrical and electronic fields. To
this end and in addition to other activities, IEC publishes International Standards, Technical Specifications,
Technical Reports, Publicly Available Specifications (PAS) and Guides (hereafter referred to as “IEC
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in the subject dealt with may participate in this preparatory work. International, governmental and non-
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with the International Organization for Standardization (ISO) in accordance with conditions determined by
agreement between the two organizations.
2) The formal decisions or agreements of IEC on technical matters express, as nearly as possible, an international
consensus of opinion on the relevant subjects since each technical committee has representation from all
interested IEC National Committees.
3) IEC Publications have the form of recommendations for international use and are accepted by IEC National
Committees in that sense. While all reasonable efforts are made to ensure that the technical content of IEC
Publications is accurate, IEC cannot be held responsible for the way in which they are used or for any
misinterpretation by any end user.
4) In order to promote international uniformity, IEC National Committees undertake to apply IEC Publications
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between any IEC Publication and the corresponding national or regional publication shall be clearly indicated in
the latter.
5) IEC itself does not provide any attestation of conformity. Independent certification bodies provide conformity
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services carried out by independent certification bodies.
6) All users should ensure that they have the latest edition of this publication.
7) No liability shall attach to IEC or its directors, employees, servants or agents including individual experts and
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expenses arising out of the publication, use of, or reliance upon, this IEC Publication or any other IEC
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8) Attention is drawn to the Normative references cited in this publication. Use of the referenced publications is
indispensable for the correct application of this publication.
9) Attention is drawn to the possibility that some of the elements of this IEC Publication may be the subject of
patent rights. IEC shall not be held responsible for identifying any or all such patent rights.
International Standard IEC 62418 has been prepared by IEC technical committee 47:
Semiconductor devices.
The text of this standard is based on the following documents:
FDIS Report on voting
47/2043/FDIS 47/2050/RVD

Full information on the voting for the approval of this standard can be found in the report on
voting indicated in the above table.
This publication has been drafted in accordance with the ISO/IEC Directives, Part 2.

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SIST EN 62418:2010
– 4 – 62418 © IEC:2010
The committee has decided that the contents of this publication will remain unchanged until
the stability date indicated on the IEC web site under "http://webstore.iec.ch" in the data
related to the specific publication. At this date, the publication will be
• reconfirmed,
• withdrawn,
• replaced by a revised edition, or
• amended.

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SIST EN 62418:2010
62418 © IEC:2010 – 5 –
SEMICONDUCTOR DEVICES –
METALLIZATION STRESS VOID TEST



1 Scope
This International Standard describes a method of metallization stress void test and
associated criteria. It is applicable to aluminium (Al) or copper (Cu) metallization.
This standard is applicable for reliability investigation and qualification of semiconductor
process.
2 Test equipment
A calibrated hot chuck or thermal chamber is required to subject the wafers or packaged test
structures to the specified temperature (±5 °C) for the specified time. For resistance
measurements dedicated equipment is needed. For void inspection deprocessing equipment
is required to remove the scratch protection layer. The inspections are performed with a
scanning electron microscope (SEM).
3 Test structure
3.1 Test structure patterns
Test structures shall be used for all metal layers which have to be inspected and several
different types of structure may be used. The following two types of test structures are
applicable for this test standard.
NOTE For metallization without refractory shunt layers reflective notching at steps can occur in test structures
with underlying topography, which will therefore tend to indicate a relatively worse stress-voiding behaviour.
3.2 Line pattern
Parallel lines which are patterned at the minimum linewidth allowed by design form an
appropriate test structure. Unless otherwise specified a minimum length of 500 μm and a total
length of 1 cm to 1 000 cm are recommended condition. Single long isolated lines are
recommended because stress voiding is often sensitive to line-to-line separation.
NOTE 1 Narrow lines are susceptible for stress voiding because the stress in the metal is typically higher in
narrower lines than in wider lines.
NOTE 2 The line length should be sufficient to insure that void nucleation sites will exist.
3.3 Via chain pattern
3.3.1 Pattern types
A via chain pattern is applicable as a test structure. For technology investigations a Kelvin-
pattern for four-point measurements may also be used.
3.3.2 Pattern for aluminium (Al) process
Via chains need to consist of a pattern of vias connected by minimum linewidth. The
recommended number of vias is between 1 000 and 100 000. It is recommended to use
isolated and long minimum linewidths.

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SIST EN 62418:2010
– 6 – 62418 © IEC:2010
3.3.3 Pattern for copper (Cu) process
For Cu metallization the following structures are applicable:
a) via chains with top and bottom metal segments with minimum allowed width;
b) via chains with either the top or the bottom metal segment at minimum allowed width, and
the other segment at the maximum width allowed for a single via;
c) vias chains with both top and bottom metal segments at the maximum width allowed for a
single via;
d) Kelvin via structures, with various widths for top and bottom metal.
Chains with 1 000 – 100 000 vias are recommended.
4 Stress temperature
To evaluate the impact of stress voiding on chip reliability under use conditions, accelerated
testing is needed to generate voiding. The acceleration factor can be strongly affected by the
factors listed in Annex B and Annex C. Therefore, it is recommended to determine empirically
the temperature range for accelerated testing which will maximize voiding. Recommended
temperature ranges are given in 5.2 and 5.3.
5 Procedure
5.1 Stress void evaluation methods
Two methods are specified for the metallization stress void test: a resistance measurement
method and a visual inspection method.
– The resistance measure method is the default method.
– The inspection method is applicable for use as a verification when no stress voiding is
expected. It cannot be used for lifetime extrapolations. This method is not applicable to Cu
metallization. The inspection method shall not be used in case the visibility of voids is
insufficient (see Note 2.)
NOTE 1 The test method most likely to detect sensitivity to stress voiding and the one most usually conducted is
constant temperature (isothermal) aging, i.e., annealing or baking at temperatures between the passivation
deposition temperature and the intended use temperature of the product.
NOTE 2 This is the case for e.g. metallization with multiple metal levels, where the lower levels are not clearly
visible, masking of voids by other process features.
5.2 Resistance measurement method
This method assumes the void growth and therefore resistance changes can be modelled, to
1
obtain an acceleration factor for void growth [1, 2] . Unless otherwise specified, the
temperature condition shall be determined within the range of 150 °C to 275 °C. Samples
need to be separated into each temperature condition group and each group to be baked at
the specified temperature. The procedure for resistance measurement is the following.
a) Measure the resistance of the metal line or via chain. Resistance measurements shall be
made at currents that minimize joule heating.
b) Bake the samples. Unless otherwise specified three temperatures are recommended to
determine the parameters for the extrapolation model. When these parameters are known
it is sufficient to test at a single temperature. In some cases, three temperatures may not
be enough if the temperature range is not chosen correctly - there could be an inflection
point in the activation energy versus temperature curve. If zero or very few failures are
___________
1
 Figures in square brackets refer to the Bibliography.

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SIST EN 62418:2010
62418 © IEC:2010 – 7 –
observed it is not possible to determine an activation energy, and a value can be selected
from the literature.
c) Measure the resistance. The samples may be cooled to room temperature for the
resistance test. Cool in less than 2 h to room temperature. (Measurement of the
resistance changes is, in principle, possible in situ at the aging temperature.)
Recommended read points: 168 h, 500 h, 1 000 h.
NOTE Resistance measurements can extend beyond 2 000 h if saturation of void growth is desired.
d) Calculate the relative change in resistance, as a percentage of the line-resistance prior to
the bake, ΔR (%).
e) Calculate the failure rate (number of failed samples/total sample size). For failure criterion
see Clause 6.
f) Determine the total length of metal line inspected.
g) If necessary, inspect failed samples to confirm the failure mode (see 5.3 for Al and e.g. [3]
for Cu).
5.3 Inspection method
The inspection method consists of the following steps.
a) Bake the samples at a specified temperature for a specified time. The recommended
temperature is 200 °C for Al metallization. Recommended read points: 0 h, 168 h, 500 h,
1 000 h. Because the maximum void initiation and growth depends on the bake
temperature, it is recommended to test at more than one temperature. The recommended
temperature range is 150 °C to 275 °C for Al. Baking times can extend beyond 2 000 h if
saturation of void growth is desired.
b) Remove the scratch protection layer with standard deprocessing techniques. If a lower
level of metallization needs to be inspected, remove all other layers to expose the desired
metallization level.
NOTE Deprocessing for Al technologies can be done with e.g. RIE (reactive-ion etching) etch for plasma
nitride/oxynitride/TEOS (incl. TiN), H O (50 °C) for Ti/TiN barrier layers, and PES (Phosphoric Acid, Acetic Acid,
2 2
Nitric Acid) etch for Al.
c) The sample shall not be sputtered with a carbon or gold layer prior to mounting in the
Scanning Electron Microscope (SEM).
d) Place the sample in the SEM, perpendicular to the incident electron beam.
e) Adjust the magnification of the SEM, such that voids down to class A (see Table 1) can be
observed. Count the number of voids in the metal lines. Both wedge shaped voids and slit
shaped voids shall be counted.
f) Perform detailed inspection at an appropriate magnification of the voids observed, to
classify these in accordance with Table 1.
g) Determine the total length of metal line inspected.
h) Calculate the densities of Class A, Class B, and Class C voids N , N , N (in voids per cm)
A B C
with 60 % confidence using Poisson statistics.
In order to classify the severity of the voids observed, the following classification scheme is
used:
Table 1 – Void classification
Class Void size/linewidth
Not counted <10 %
A ≥10 %, …, <25 %
B ≥25 %, …, <50 %
C ≥50 %

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