SIST IEC 60104:1999

IEC 61189-3-913
®

Edition 1.0 2016-01
INTERNATIONAL
STANDARD
NORME
INTERNATIONALE
colour
inside


Test methods for electrical materials, printed boards and other interconnection
structures and assemblies –
Part 3-913: Test method for thermal conductivity of printed circuit boards for
high-brightness LEDs

Méthodes d'essai pour les matériaux électriques, les cartes imprimées et autres
structures d'interconnexion et ensembles –
Partie 3-913: Méthodes d'essai pour la conductivité thermique des circuits
imprimés pour les LED à forte luminosité

IEC 61189-3-913:2016-01(en-fr)

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IEC 61189-3-913

®


Edition 1.0 2016-01




INTERNATIONAL



STANDARD




NORME



INTERNATIONALE
colour

inside










Test methods for electrical materials, printed boards and other interconnection

structures and assemblies –

Part 3-913: Test method for thermal conductivity of printed circuit boards for


high-brightness LEDs



Méthodes d'essai pour les matériaux électriques, les cartes imprimées et autres


structures d'interconnexion et ensembles –

Partie 3-913: Méthodes d'essai pour la conductivité thermique des circuits

imprimés pour les LED à forte luminosité










INTERNATIONAL

ELECTROTECHNICAL

COMMISSION


COMMISSION

ELECTROTECHNIQUE


INTERNATIONALE




ICS 31.180 ISBN 978-2-8322-3104-3



Warning! Make sure that you obtained this publication from an authorized distributor.

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® Registered trademark of the International Electrotechnical Commission
Marque déposée de la Commission Electrotechnique Internationale

---------------------- Page: 3 ----------------------
– 2 – IEC 61189-3-913:2016 © IEC 2016
CONTENTS
FOREWORD . 4
1 Scope . 6
2 Normative references . 6
3 Terms and definitions . 6
4 Pre–conditioning . 6
5 Test methods . 6
5.1 General . 6
5.2 Thermal conductivity . 6
5.2.1 Measurement of thermal resistance on the plane . 6
5.2.2 Measurement of thermal resistance across the thickness . 8
Annex A (normative) Boards and panels . 13
A.1 Panel and board sizes . 13
A.1.1 Board size . 13
A.1.2 Allowance of dimensions . 13
A.1.3 Perforation and slit . 14
A.1.4 V-cut. 14
A.2 Total board thickness . 15
A.3 Holes . 16
A.3.1 Insertion holes and vias . 16
A.3.2 Datum hole . 19
A.3.3 Assembly hole (through-hole without wall plating) . 19
A.4 Conductor . 19
A.4.1 Width of conductor pattern and its allowance . 19
A.4.2 Distance between conductors and its allowance . 20
A.4.3 Thickness of the insulating layer . 21
A.5 Printed contact . 21
A.5.1 Allowance of the distance between the centers of two adjacent printed
contacts . 21
A.5.2 Allowance of the terminal width of printed contacts . 22
A.5.3 Shift of the center of printed contacts on the front and back sides of a
board . 22
A.6 Land pattern . 23
A.6.1 Allowance of the distance between the centers of two lands . 23
A.6.2 Allowance of a land width . 23
A.6.3 Land diameter and its allowance for BGA/CSP . 24
A.7 Fiducial mark and mark for component positioning . 25
A.7.1 Typical form and size of the fiducial mark . 25
A.7.2 Dimensional allowance of fiducial mark and component positioning mark . 26
A.7.3 Position allowance of the component positioning mark. 26
A.8 Interlayer connection – Copper plating . 26
Annex B (normative) Equilibrium test . 27
Bibliography . 28

Figure 1 – Illustration of an apparatus for the thermal conductivity test . 10
Figure 2 – Surface layer specimen pattern for thermal conductivity test . 11
Figure 3 – Test equipment for thermal resistance to the thickness direction . 12

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IEC 61189-3-913:2016 © IEC 2016 – 3 –
Figure A.1 – Board arrangement in a panel . 13
Figure A.2 – Distances from the datum point to perforation and slit . 14
Figure A.3 – Distance from the datum point to the V-cut . 15
Figure A.4 – Allowance of position off-set of V-cuts on front and back surfaces . 15
Figure A.5 – PWB board with symbol mark, solder resist, copper foil and plating . 16
Figure A.6 – Positions of component insertion holes . 17
Figure A.7 – Distance between the wall of a hole and the board edge . 18
Figure A.8 – Wall of a hole and the minimum designed spacing to the inner conductor . 19
Figure A.9 – Width of finished conductor . 20
Figure A.10 – Distance between conductor and board edge . 21
Figure A.11 – Thickness of the insulating layer . 21
Figure A.12 – Distance between centers of terminals of printed contacts . 22
Figure A.13 – Terminal width of a printed contact . 22
Figure A.14 – Shift of the center of printed contacts on front and back sides of a board . 23
Figure A.15 – Land pattern . 23
Figure A.16 – Land width of a land pattern . 24
Figure A.17 – Land diameter of BGA/CSP formed of a conductor only . 24
Figure A.18 – Land diameter (d) of BGA/CSP formed at the opening of solder resist . 25
Figure A.19 – Examples of fiducial mark and component positioning mark . 26

Table 1 – Applied power (P) that corresponds to a range of thermal resistance
on the plane . 8
Table 2 – Applied power (P) that corresponds to a range of thermal resistance

across the thickness (K/W) . 9
Table A.1 – Panel dimensions . 13
Table A.2 – Allowance of dimensions . 14
Table A.3 – Allowance of the distances from the datum point to perforation and slit . 14
Table A.4 – Allowance of the distance from the datum point to the center of the V-cut . 15
Table A.5 – Total thickness and its allowance . 16
Table A.6 – Allowance of holes for component insertion. 16
Table A.7 – Position allowance of component insertion holes . 17
Table A.8 – Distance between the wall of a hole and board edge . 18
Table A.9 – Minimum clearance between the wall of a hole and the inner layer
conductor . 18
Table A.10 – Allowance of conductor width . 20
Table A.11 – Allowance of the distance between conductors . 20
Table A.12 – Allowance of terminal width of a printed contact . 22
Table A.13 – Allowance of terminal width of a printed contact . 23
Table A.14 – Allowance of the width of a land of a land pattern . 24
Table A.15 – Land diameter and its allowance for BGA/CSP . 25
Table A.16 – Allowance of the land diameter (d) of BGA/CSP formed at the opening of
solder resist . 25
Table A.17 – Shapes and sizes of typical fiducial marks and component positioning

marks . 26
Table A.18 – Minimum thickness of copper plating . 26

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– 4 – IEC 61189-3-913:2016 © IEC 2016
INTERNATIONAL ELECTROTECHNICAL COMMISSION
____________

TEST METHODS FOR ELECTRICAL MATERIALS, PRINTED BOARDS AND
OTHER INTERCONNECTION STRUCTURES AND ASSEMBLIES –

Part 3-913: Test method for thermal conductivity of printed
circuit boards for high-brightness LEDs

FOREWORD
1) The International Electrotechnical Commission (IEC) is a worldwide organization for standardization comprising
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8) Attention is drawn to the Normative references cited in this publication. Use of the referenced publications is
indispensable for the correct application of this publication.
9) Attention is drawn to the possibility that some of the elements of this IEC Publication may be the subject of
patent rights. IEC shall not be held responsible for identifying any or all such patent rights.
International Standard IEC 61189-3-913 has been prepared by IEC technical committee 91:
Electronics assembly technology.
This first edition cancels and replaces the first edition of IEC PAS 61189-3-913 published in
2011. This edition constitutes a technical revision. This edition focused only on the test
methods for thermal conductivity specific to printed circuit boards for high-brightness LEDs.
The text of this standard is based on the following documents:
FDIS Report on voting
91/1304A/FDIS 91/1328/RVD

Full information on the voting for the approval of this standard can be found in the report on
voting indicated in the above table.

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IEC 61189-3-913:2016 © IEC 2016 – 5 –
A list of all parts in the IEC 61189, published under the general title Test methods for
electrical materials, printed boards and other interconnection structures and assemblies, can
be found on the IEC website.
This publication has been drafted in accordance with the ISO/IEC Directives, Part 2.
The committee has decided that the contents of this publication will remain unchanged until
the stability date indicated on the IEC website under "http://webstore.iec.ch" in the data
related to the specific publication. At this date, the publication will be
• reconfirmed,
• withdrawn,
• replaced by a revised edition, or
• amended.

IMPORTANT – The 'colour inside' logo on the cover page of this publication indicates
that it contains colours which are considered to be useful for the correct
understanding of its contents. Users should therefore print this document using a
colour printer.

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– 6 – IEC 61189-3-913:2016 © IEC 2016
TEST METHODS FOR ELECTRICAL MATERIALS, PRINTED BOARDS AND
OTHER INTERCONNECTION STRUCTURES AND ASSEMBLIES –

Part 3-913: Test method for thermal conductivity of printed
circuit boards for high-brightness LEDs



1 Scope
This part of IEC 61189 specifies the test methods for thermal conductivity specific to printed
circuit boards for high-brightness LEDs. The test applies to printed circuit boards for high-
brightness LEDs with surface mounted LEDs or with device embedded LEDs in electronic
control devices (ECDs).
2 Normative references
The following documents, in whole or in part, are normatively referenced in this document and
are indispensable for its application. For dated references, only the edition cited applies. For
undated references, the latest edition of the referenced document (including any
amendments) applies.
IEC 60194, Printed board design, manufacture and assembly – Terms and definitions
IEC 62326-20, Printed boards – Part 20: Printed circuit boards for high-brightness LEDs
3 Terms and definitions
For the purposes of this document, the terms and definitions given in IEC 60194 apply, unless
otherwise specified.
4 Pre–conditioning
Pre-conditioning described in a) or b) below shall be carried out in accordance with the
specific standard.
a) Leave a specimen for 24 h in the standard condition.
b) Leave a specimen for 60 min in a thermostat chamber at 85 °C and then leave the
specimen for 24 ± 4 h in the standard atmospheric condition.
5 Test methods
5.1 General
In this standard, the following test methods are specified in order to classing the printed
circuit board in accordance with Table 1 in IEC 62326-20.
5.2 Thermal conductivity
5.2.1 Measurement of thermal resistance on the plane
In this subclause, the measurement of thermal resistance on the plane (horizontal direction of
the specimen) is addressed as follows.

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IEC 61189-3-913:2016 © IEC 2016 – 7 –
a) Apparatus
Use the apparatus specified in EIA/JEDEC STD 51-2, or equivalent. The equipment shall
have a set of a specimen and a thermocouple in the centre of a cubic chamber of 30 cm
side length. An apparatus is shown in Figure 1.
b) Specimen
Unless otherwise specified, use the specimen illustrated in Figure 2. All the dimensions in
Figure 2 shall be requirements. This specimen uses a TEG chip (5 mm × 5 mm) with a
temperature measuring sensor, which is wire-bonded to the centre of the specimen board
as a heat source. The detail specification of the printed board shall be in accordance with
Annex A.
c) Pre-conditioning
Pre-conditioning shall be in accordance with Clause 4. And, the test specimen shall be
fixed horizontally in the chamber of the equipment.
d) Thermal resistance and heat transfer parameter on the plane (horizontal direction of the
specimen). The following procedure shall be respected:
• provide a specimen assembled with a heater with a TEG chip with a temperature
measuring sensor;
• specify the temperature coefficient of the sensor prior to the measurement;
• operate the heater and arrange the applied power (P) based upon the range of thermal
resistance on the plane (horizontal direction of the specimen) as shown in Table 1;
• measure the temperature of the TEG chip with a temperature measuring sensor (T )
s
and the temperature inside the chamber (T ) after the temperature of the TEG chip
a
with a temperature measuring sensor has reached a stable state;
• calculate the thermal resistance on the plane (horizontal direction of the specimen)
(R ) with the following equation:
p
R = (T – T ) / P
p s a
• using the thermal resistance (R ), calculate the thermal transfer parameter (he) by the
p
following equation:
1
2
he = W/m K
R × 0,002 5
p
Equilibrium verification shall be in accordance with Annex B.

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– 8 – IEC 61189-3-913:2016 © IEC 2016
Table 1 – Applied power (P) that corresponds to a range of thermal
resistance on the plane
Range of thermal resistance
Applied power on the plane
(horizontal direction of the specimen) (R )
p
W K/W
0,1 300 > R
p
0,2 200 < R < 300
p
0,3 150 < R < 200
p
0,4 100 < R < 150
p
0,75
60 < R < 100
p
1,0 30 < R < 60
p
2,0 20 < R < 30
p
3,0 15 < R < 20
p
5,0 5 < R < 15
p
10,0 < 5
R
p

5.2.2 Measurement of thermal resistance across the thickness
In this subclause, the measurement of thermal resistance across the thickness is addressed
as follows.
a) Apparatus
The testing apparatus is as shown in Figure 3. The apparatus shall consist of a metal
block (aluminium or copper) which can hold the specimen specified in 5.2.1 b) and a
cooling system to keep the temperature of the metal block constant.
b) Specimen
Specimen shall be as specified in 5.2.1 b).
c) Pre-conditioning
Pre-conditioning shall be in accordance with Clause 4.
d) Test
The procedure shall be as follows:
• provide a specimen, which is screwed to the metal block, assembled with a heater that
contains a TEG chip with a temperature measuring sensor;
• specify the temperature coefficient of the sensor prior to the measurement;
• apply thermal conductive materials such as thermal grease between the specimen and
the metal block to reduce thermal resistivity;
• install a thermocouple within a 10 mm distance from the edge of the specimen;
• install another thermocouple in the water sink;
• fix the metal block to the cooling system;
• keep the water temperature constant by the water-cooled system as shown in
Figure 3;
• operate the heater and arrange the applied power (P) based on the thermal resistance
across the thickness, as shown in Table 2;
• measure the temperature of the TEG chip with a temperature measuring sensor (T )
s
and the temperature on the metal block (T ) as soon as the temperature of the TEG
b
chip with a temperature measuring sensor has reached the stable state;
• calculate the thermal resistance across the thickness (R ) by the following equation:
t

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IEC 61189-3-913:2016 © IEC 2016 – 9 –
R = (T − T ) /P (K/W)
t s b
The thermal conductivity parameter (Ke) shall be calculated with the following equation using
R .
t
t
2
Ke = W/m K
−5
R × 2,5 ×10
t
where
t is the thickness (m);
–5 2
2,5 × 10 (m ) is the area of the TEG chip with a temperature measuring sensor.
Table 2 – Applied power (P) that corresponds to a range of thermal
resistance across the thickness (K/W)
Applied power Range of thermal resistance across the thickness (R )
t
W K/W
0,1
300 > R
t
0,2
200 < R < 300
t
0,3 150 < R < 200
t
0,4 100 < R < 150
t
0,75 60 < R < 100
t
1,0
30 < R < 60
t
2,0
20 < R < 30
t
3,0 15 < R < 20
t
5,0 5 < R < 15
t
10,0
R < 5
t

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– 10 – IEC 61189-3-913:2016 © IEC 2016
Dimensions in millimetres
Thermocouple
Specimen
Arrange as to the heating
TEG (test equipment
group) to the center of the
cabinet
...